Add project 05

This commit is contained in:
lucky-vers 2024-02-14 00:44:02 +05:30
parent 723381e63c
commit 3d68f8760a
6 changed files with 87 additions and 10 deletions

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@ -27,10 +27,44 @@ CHIP CPU {
// the current program (reset==0).
OUT outM[16], // M value output
writeM, // Write to M?
writeM, // Write to M?
addressM[15], // Address in data memory (of M)
pc[15]; // Address of next instruction
PARTS:
//// Replace this comment with your code.
Not(in=instruction[15], out=Ainstruction);
Not(in=Ainstruction, out=Cinstruction);
And(a=Cinstruction, b=instruction[5], out=ALUtoA); // C-inst and dest to A-reg?
Mux16(a=instruction, b=ALUout, sel=ALUtoA, out=Aregin);
Or(a=Ainstruction, b=ALUtoA, out=loadA); // load A if A-inst or C-inst&dest to A-reg
ARegister(in=Aregin, load=loadA, out=Aout);
Mux16(a=Aout, b=inM, sel=instruction[12], out=AMout); // select A or M based on a-bit
And(a=Cinstruction, b=instruction[4], out=loadD);
DRegister(in=ALUout, load=loadD, out=Dout); // load the D register from ALU
ALU(x=Dout, y=AMout, zx=instruction[11], nx=instruction[10],
zy=instruction[9], ny=instruction[8], f=instruction[7],
no=instruction[6], out=ALUout, zr=ZRout, ng=NGout); // calculate
// Set outputs for writing memory
Or16(a=false, b=Aout, out[0..14]=addressM);
Or16(a=false, b=ALUout, out=outM);
And(a=Cinstruction, b=instruction[3], out=writeM);
// calc PCload & PCinc - whether to load PC with A reg
And(a=ZRout, b=instruction[1], out=jeq); // is zero and jump if zero
And(a=NGout, b=instruction[2], out=jlt); // is neg and jump if neg
Or(a=ZRout, b=NGout, out=zeroOrNeg);
Not(in=zeroOrNeg, out=positive); // is positive (not zero and not neg)
And(a=positive, b=instruction[0], out=jgt); // is pos and jump if pos
Or(a=jeq, b=jlt, out=jle);
Or(a=jle, b=jgt, out=jumpToA); // load PC if cond met and jump if cond
And(a=Cinstruction, b=jumpToA, out=PCload); // Only jump if C instruction
Not(in=PCload, out=PCinc); // only inc if not load
PC(in=Aout, inc=PCinc, load=PCload, reset=reset, out[0..14]=pc);
}

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@ -5,17 +5,20 @@
/**
* The Hack computer, consisting of CPU, ROM and RAM.
* When reset is 0, the program stored in the ROM executes.
* When reset is 1, the program's execution restarts.
* When reset is 1, the program's execution restarts.
* Thus, to start running the currently loaded program,
* set reset to 1, and then set it to 0.
* set reset to 1, and then set it to 0.
* From this point onwards, the user is at the mercy of the software:
* Depending on the program's code, and whether the code is correct,
* the screen may show some output, the user may be expected to enter
* some input using the keyboard, or the program may do some procerssing.
* some input using the keyboard, or the program may do some procerssing.
*/
CHIP Computer {
IN reset;
PARTS:
//// Replace this comment with your code.
ROM32K(address=pc, out=instruction);
CPU(inM=memOut, instruction=instruction, reset=reset, outM=outM,
writeM=writeM, addressM=addressM, pc=pc);
Memory(in=outM, load=writeM, address=addressM, out=memOut);
}

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@ -2,7 +2,7 @@
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/Memory.hdl
/**
/**
* The Memory chip implements the complete address space of the Hack data memory,
* including RAM, memory mapped screen, and memory mapped keyboard.
* Outputs the value of the memory location specified by the address input.
@ -13,11 +13,16 @@
* Access to address 0 to 16383 (0x0000 to 0x3FFF) results in accessing the RAM;
* Access to address 16384 to 24575 (0x4000 to 0x5FFF) results in accessing the Screen memory map;
* Access to address 24576 (0x6000) results in accessing the Keyboard memory map.
*/
*/
CHIP Memory {
IN in[16], load, address[15];
OUT out[16];
PARTS:
//// Replace this comment with your code.
DMux4Way (in=load, sel=address[13..14], a=ram1, b=ram2, c=loadscreen, d=loadkb);
Or (a=ram1, b=ram2, out=loadram);
RAM16K (in=in, load=loadram, address=address[0..13], out=outram);
Screen (in=in, load=loadscreen, address=address[0..12], out=outscr);
Keyboard (out=outkb);
Mux4Way16(a=outram, b=outram, c=outscr, d=outkb, sel=address[13..14], out=out);
}

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@ -0,0 +1,35 @@
| in |load | address | out |
| -1 | 1 | 000000000000000 | 0 |
| -1 | 1 | 000000000000000 | -1 |
| 9999 | 0 | 000000000000000 | -1 |
| 9999 | 0 | 000000000000000 | -1 |
| 9999 | 0 | 010000000000000 | 0 |
| 9999 | 0 | 100000000000000 | 0 |
| 2222 | 1 | 010000000000000 | 0 |
| 2222 | 1 | 010000000000000 | 2222 |
| 9999 | 0 | 010000000000000 | 2222 |
| 9999 | 0 | 010000000000000 | 2222 |
| 9999 | 0 | 000000000000000 | -1 |
| 9999 | 0 | 100000000000000 | 0 |
| 9999 | 0 | 000000000000001 | 0 |
| 9999 | 0 | 000000000000010 | 0 |
| 9999 | 0 | 000000000000100 | 0 |
| 9999 | 0 | 000000000001000 | 0 |
| 9999 | 0 | 000000000010000 | 0 |
| 9999 | 0 | 000000000100000 | 0 |
| 9999 | 0 | 000000001000000 | 0 |
| 9999 | 0 | 000000010000000 | 0 |
| 9999 | 0 | 000000100000000 | 0 |
| 9999 | 0 | 000001000000000 | 0 |
| 9999 | 0 | 000010000000000 | 0 |
| 9999 | 0 | 000100000000000 | 0 |
| 9999 | 0 | 001000000000000 | 0 |
| 9999 | 0 | 010000000000000 | 2222 |
| 1234 | 1 | 001001000110100 | 0 |
| 1234 | 1 | 001001000110100 | 1234 |
| 1234 | 0 | 010001000110100 | 0 |
| 1234 | 0 | 110001000110100 | 0 |
| 2345 | 1 | 010001101000101 | 0 |
| 2345 | 1 | 010001101000101 | 2345 |
| 2345 | 0 | 000001101000101 | 0 |
| 2345 | 0 | 100001101000101 | 0 |

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@ -1 +1 @@
/home/verma/Projects/nand2tetris/projects/04/fill
/home/verma/Projects/nand2tetris/projects/05