Commit graph

548 commits

Author SHA1 Message Date
Esun Kim
ff3209d088
Manually synced from upstream (#3650)
* Synced

* No absl

* Fix warning

* no_sanitize revised
2026-08-12 08:25:39 -07:00
Esun Kim
b89fb3e06e
Tune hard_swish_test.cc (#3640)
* Tune hard_swish_test.cc

* Fix 2

* Better make output

* Fix format
2026-07-29 15:34:53 +00:00
David Davis
8f1f3b2623
WHILE operator input/output copy fix (#3633)
@tensorflow/micro

Remove extraneous tensor copy operation after first invocation of condition subgraph.

Move copy of operator inputs to outputs, such that it occurs before the first invocation of the condition subgraph. This preserves the operator inputs when one or more of them is the output of DECODE, and alternate decompression memory is in use. This is because the output of DECODE is for immediate consumption by the next operator in the graph (WHILE), yet it is possible for the WHILE subgraph invocations to share memory with the original DECODE output.

Update the unit test for multiple invocations of the condition and body subgraphs.

When copying tensors between operator inputs/outputs and subgraph inputs/outputs, check if the source and destination tensors share memory.

bug=fixes #3632
2026-07-20 17:58:59 +00:00
Esun Kim
5750228374
Add Reset support to CircularBuffer op (#3618)
* Add reset support to circular_buffer

* Format
2026-07-08 21:34:43 +00:00
Esun Kim
bc0e8c658b
Re-enable 3D x 2D BatchMatMul dimension collapse for adj_x=true (#3599)
* Re-enable 3D x 2D BatchMatMul dimension collapse for adj_x=true

* Code style
2026-07-08 15:32:05 +00:00
Måns Nilsson
acc13e42eb
Update CMSIS-NN download (#3607)
- Adapt build logic to not build float support since TFLM does not use
  the CMSIS-NN CMake path.

- Zero-initialize the cmsis_nn_lstm_context used by the int8 and int16
  unidirectional sequence LSTM paths so optional fields such as hidden_state do
  not contain stack garbage.

Change-Id: I5b44a3a231eb19023e004a5652b207930853648f

Signed-off-by: Måns Nilsson <mans.nilsson@arm.com>
2026-06-24 04:03:35 +00:00
Esun Kim
7ca66d18e7
Ensure int64 accumulation for bias-less 16x8 ops in TFLM kernels (#3598) 2026-06-16 23:58:19 +00:00
Esun Kim
63819227bc
Fix cmsis-nn pooling (#3584) 2026-06-01 16:24:20 +00:00
Esun Kim
cc99d0597f
Removed batch_size assert in depthwise_conv (#3562) 2026-05-27 16:41:22 +00:00
Esun Kim
2ba41b0f3e
Fixed rank support in pad and min/max (#3563) 2026-05-27 16:41:17 +00:00
Esun Kim
7914a2d7a1
Clean-up unused bzl load (#3576) 2026-05-26 22:55:55 +00:00
Ryan Kuester
068c6a59b6
build(bazel): inject tflite_micro shim via tflm_py_* wrappers (#3573)
Python targets in this repository import one another under the
"tflite_micro" package namespace, which //:tflite_micro_shim synthesizes
at import time. The shim is required under Bzlmod, where the main
repository's runfiles root is the fixed name "_main" rather than the
module name, so the "tflite_micro" prefix no longer resolves on its own.
Every such target therefore had to list //:tflite_micro_shim in its
deps, which was repetitive and easy to forget.

Add tflm_py_library, tflm_py_test, and tflm_py_binary wrappers in a new
//python:py_rules.bzl that inject the shim dependency automatically,
following the naming convention of the existing tflm_cc_* wrappers, and
document the shim's rationale there. Convert every target that
previously listed the shim to the corresponding wrapper and drop the
explicit dependency. The dependency graph is unchanged; only the means
by which the shim is attached differs.
2026-05-26 19:51:58 +00:00
Esun Kim
cf8c42a16f
Align Conv INT16 accumulator logic with FullyConnected (#3537)
* Align Conv INT16 accumulator logic with FullyConnected

* Applied to optimized kernels

* Format fix
2026-05-06 13:02:51 +00:00
Esun Kim
51bee03bed
Default to 64-bit accumulation for 16x8 Fully Connected without bias (#3522) 2026-04-09 18:35:03 +00:00
Esun Kim
c36885e9e6
[Fix] Batch MatMul Op (#3413)
* Added BatchMatMulOpTestFloat32Test_BatchSizeTwo_Broadcast_LHSAdjoint

Added BatchMatMulOpTestFloat32Test_BatchSizeTwo_Broadcast_RHSAdjoint

* Fixed cmsis_nn/batch_matmul.cc
2026-04-09 18:34:59 +00:00
Nicolás Arrieta Larraza
f5302ed4fa
Add 16bit xtensa depthwise conv kernel support (#3481)
* Added 16x8 xtensa depthwise conv kernel

* Added int16 support only for HIFI5

* Code formatting
2026-03-18 16:23:13 +00:00
Esun Kim
807c35d6a9
Bazel Module (#3364)
* Work

* Review update

* Enabled tests

* Bazel: Suppress warnings from external repositories

* Fixed whl_test

* Formatted

* More format
2026-02-11 14:11:47 -08:00
Esun Kim
183da3e302
Typo in code (#3447)
* Typo in code

* Format
2026-02-11 20:34:42 +00:00
Esun Kim
d7f46b6fb7
[Doc] Fix typos (#3446)
* Fix typos

* Typos

* More

* Last
2026-02-11 17:18:49 +00:00
unmeshna017
5b93e5b3fe
Added activation function for CREF code of transpose_conv operator. (#3278) 2026-02-10 15:23:45 +00:00
unmeshna017
ef48280f08
Updated the CREF code of the resize nearest neighbor operator to use the half_pixel_centers attribute from params. (#3279) 2026-02-10 15:23:00 +00:00
Esun Kim
88f8587b3f
[T2] Refactor Group 8: Decode (#3375)
* Refactor t2-8

* Fix
2026-02-03 17:50:27 +00:00
Esun Kim
63d4dbd332
[T2] Refactor Group 9z: Compression (#3393)
* Refactor t2-9z

Refactor t2-11z

Refactor t2-19z

Refactor t2-7z

* Fix

* Review
2026-02-03 17:50:04 +00:00
Esun Kim
a6cd602b1a
[T2] Refactor Group 19 (#3386)
* Refactor t2-19

* Undo
2026-02-02 17:51:09 +00:00
Esun Kim
95c1e6534d
[T2] Refactor Group 16 (#3383)
* Refactor t2-16

* Fix

* Fix
2026-02-02 17:50:50 +00:00
Esun Kim
e44f83652c
[T2] Refactor Group 11 (#3378)
* Refactor t2-11

* Undo
2026-02-02 17:50:01 +00:00
Esun Kim
1712dc2c33
[T2] Refactor Group 9 (#3376)
* Refactor t2-9

* Undo
2026-02-02 17:49:36 +00:00
Esun Kim
83525e927e
[T2] Refactor Group 7 (#3374)
* Refactor t2-7

* Fix

* Undo conv_test
2026-02-02 17:49:11 +00:00
Esun Kim
d2c879319c
Refactor t2-13 (#3380) 2026-01-30 23:27:34 +00:00
Esun Kim
56943c5f59
[T2] Refactor Group 18 (#3385)
* Refactor t2-18

* Fix
2026-01-30 18:26:38 +00:00
Esun Kim
9eca5ef53d
Refactor t2-17 (#3384) 2026-01-30 18:13:44 +00:00
Esun Kim
9b4cd60882
[T2] Refactor Group 15 (#3382)
* Refactor t2-15

* Fix
2026-01-30 18:13:27 +00:00
Esun Kim
0389008cd7
Refactor t2-14 (#3381) 2026-01-30 18:13:09 +00:00
Esun Kim
6d906db645
Refactor t2-12 (#3379) 2026-01-30 17:38:14 +00:00
Esun Kim
2a75554d7f
Refactor t2-10 (#3377) 2026-01-30 17:37:47 +00:00
Esun Kim
2af49119dc
Refactor t2-6 (#3373) 2026-01-30 17:36:53 +00:00
Esun Kim
41a80afaa4
[Dep] Upgraded Flatbuffer to 25.9.23 (#3296)
* flatbuffer-25.9.23

* Patch 1

* No dynamic allocation patch to Flatbuffer

* Individual ModelBuilder

* Fix

* Patch

* One more removal
2026-01-27 22:12:21 +00:00
Shlomi Regev
254211d449
Correctly initialize ae_int8x8 zero point vectors by explicitly pac… (#3349)
* Correctly initialize `ae_int8x8` zero point vectors by explicitly packing scalar values.

The implicit broadcast doesn't compile with toolchain version RI-2020.5-linux and a hifi5 core.

BUG=478153404

* refactor: simplify Xtensa `ae_int8x8` zero vector initialization using `AE_MOVDA8`.

* Simplify
2026-01-27 15:38:44 +00:00
Esun Kim
2aa6e12979
[CI] Reformat (#3347)
* Clean-up BUILD

* Added pyproject.toml

* Format gen

* Fix

* Fix format

* Fix
2026-01-24 21:13:38 -08:00
Esun Kim
ee42e1d5b3
Format (#3346) 2026-01-24 20:06:04 -08:00
Esun Kim
f6baf77eb5
[CI] windows 2 (#3345)
* Fixes

* Exclude

* Exclude more
2026-01-24 18:15:48 -08:00
Esun Kim
f1f920edf8
Fixes (#3343) 2026-01-24 17:36:45 -08:00
Esun Kim
e0c86f133e
fixes (#3342) 2026-01-24 17:10:55 -08:00
David Davis
5cdb80a703
Reduce output of LUT compression tests (#3326)
@tensorflow/micro

Enable/disable output of extra debug messages through a single #define.  Default disabled.

bug=n/a
2026-01-24 00:39:34 +00:00
Shlomi Regev
f219fef927
Solve compiler errors in decode op (Xtensa) (#3305)
When building with old Xtensa toolchains, the compiler throws an unused variable warning
which is treated as error (-Werror is defined by default).
The cause is ScopedMicroProfile instantiation in the decoder op. Added a dummy reference to mute the warning.

Old pre C++14 Xtensa compilers don't support ticks in preprocessor constants, e.g. 0x8000'0000
Removed the ticks.

BUG=451462435
2026-01-20 18:13:14 +00:00
Esun Kim
0efdd51a3a
Refactor: Use scratch buffers for reduce kernel (#3281) 2026-01-16 17:21:16 +00:00
Esun Kim
fd33340e06
Revert "[CI] Replaced tensorflow with tensorflow-cpu (#3261)" (#3290)
This reverts commit 9cbf6e0403.
2026-01-12 11:19:37 -08:00
Shlomi Regev
1ed47b150c
Solve compiler errors in decode op (#3284)
1. When building with old Xtensa toolchains, the compiler throw an unused variable warning
which is treated as error (-Werror is defined by default).
The cause is ScopedMicroProfile instantiation in the decoder op. Added a dummy reference to mute the warning.

2. Old pre C++14 Xtensa compilers don't support ticks in preprocessor constants, e.g. 0x8000'0000
Removed the ticks.

BUG=451462435
2026-01-12 08:50:34 +01:00
Shlomi Regev
23b7229d9c
Provide default values for uninitialized variable (#3282)
Switch-cases in decode_state_lut.cc don't assign a default value
to a local variables. On one version of ARM GCC (building for ARM cortex m33, this results in
a compiler error [-Werror=maybe-uninitialized].

BUG=451462435
2026-01-09 16:21:43 +00:00
Kunasi Ramesh
ef382bdaae
Porting Reduce_All reference operator porting from TFLite to TFLM (#3269)
* Sync files related to Reverse_V2 from TFLite

#3110

* PRelu Int16x8 support in RefC

* Fix code style in prelu_test.cc

* 1. Reverted the copyright year

* Resolved compilation error for Int8x8 test case

* Add Dynamic_Update_Slice support to TFLM

* Code style error correction

* Code style correction

* Replaced hard coded MaxDimensions to RuntimeShape::kMaxSmallSize

* 1. Added more test cases \n2.Removed unused code

* Updates for test failure on ARM

* Code style updates

* Updates on test case failure for ARM

* Updates on test case failure for ARM

* Code style updates

* Add Reduce_All reference operator support to TFLM

* Resolving HiFi build errors

---------

Co-authored-by: Esun Kim <veblush@google.com>
2026-01-08 10:34:29 -08:00