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f9fecab84e
Implement tensor decompression in op conv. Extend tests to validate operation on compressed tensors. BUG=part of #2636
134 lines
4.7 KiB
C++
134 lines
4.7 KiB
C++
/* Copyright 2024 The TensorFlow Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#ifndef TENSORFLOW_LITE_MICRO_KERNELS_CONV_H_
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#define TENSORFLOW_LITE_MICRO_KERNELS_CONV_H_
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#include <cstdint>
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#include "tensorflow/lite/c/builtin_op_data.h"
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#include "tensorflow/lite/kernels/internal/types.h"
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#include "tensorflow/lite/micro/micro_common.h"
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namespace tflite {
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struct OpDataConv {
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TfLitePaddingValues padding;
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// Cached tensor zero point values for quantized operations.
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int32_t input_zero_point;
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int32_t filter_zero_point;
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int32_t output_zero_point;
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// The scaling factor from input to output (aka the 'real multiplier') can
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// be represented as a fixed point multiplier plus a left shift.
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int32_t output_multiplier;
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int output_shift;
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// Per channel output multiplier and shift.
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int32_t* per_channel_output_multiplier;
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int32_t* per_channel_output_shift;
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// The range of the fused activation layer. For example for kNone and
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// uint8_t these would be 0 and 255.
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int32_t output_activation_min;
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int32_t output_activation_max;
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// A buffer used to store unpacked filter values. This is used if the source
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// tensor is of n-bit precision that cannot be easily processed by kernels.
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int filter_buffer_index;
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#ifdef USE_TFLM_COMPRESSION
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// scratch buffers for compressed tensors
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int weights_scratch_index;
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int bias_scratch_index;
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#endif // USE_TFLM_COMPRESSION
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};
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extern const int kConvInputTensor;
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extern const int kConvWeightsTensor;
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extern const int kConvBiasTensor;
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extern const int kConvOutputTensor;
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extern const int kConvQuantizedDimension;
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// Returns a ConvParams struct with all the parameters needed for a
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// float computation.
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ConvParams ConvParamsFloat(const TfLiteConvParams& params,
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const OpDataConv& data);
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// Returns a ConvParams struct with all the parameters needed for a
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// quantized computation.
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ConvParams ConvParamsQuantized(const TfLiteConvParams& params,
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const OpDataConv& data);
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TfLiteStatus CalculateOpDataConv(TfLiteContext* context, TfLiteNode* node,
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const TfLiteConvParams& params, int width,
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int height, int filter_width,
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int filter_height, int out_width,
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int out_height, const TfLiteType data_type,
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OpDataConv* data);
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void* ConvInit(TfLiteContext* context, const char* buffer, size_t length);
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TfLiteStatus ConvPrepare(TfLiteContext* context, TfLiteNode* node);
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// This is the most generic TFLMRegistration. The actual supported types
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// may still be target dependent. The only requirement is that every
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// implementation (reference or optimized) must define this function.
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TFLMRegistration Register_CONV_2D();
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#if defined(XTENSA)
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// Returns a TFLMRegistration struct for kernel variant that only supports
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// int8 activations and int8 weights and always calls the reference
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// implementation.
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TFLMRegistration Register_CONV_2D_INT8REF();
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#else
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inline TFLMRegistration Register_CONV_2D_INT8REF() {
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return Register_CONV_2D();
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}
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#endif // defined(XTENSA)
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#if defined(CMSIS_NN)
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// Returns a TFLMRegistration struct for kernel variant that only supports
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// int8 activations and int4 weights and uses the latency optimized
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// implementations.
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TFLMRegistration Register_CONV_2D_INT4();
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#else
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inline TFLMRegistration Register_CONV_2D_INT4() { return Register_CONV_2D(); }
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#endif // defined(CMSIS_NN)
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#if defined(CMSIS_NN) || defined(XTENSA)
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// Returns a TFLMRegistration struct for kernel variant that only supports
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// int8 activations and int8 weights and uses the latency optimized
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// implementations.
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TFLMRegistration Register_CONV_2D_INT8();
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// Returns a TFLMRegistration struct for kernel variant that only supports
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// int16 activations and int8 weights and uses the latency optimized
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// implementations.
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TFLMRegistration Register_CONV_2D_INT16();
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#else
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inline TFLMRegistration Register_CONV_2D_INT8() { return Register_CONV_2D(); }
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inline TFLMRegistration Register_CONV_2D_INT16() { return Register_CONV_2D(); }
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#endif // defined(CMSIS_NN) || defined(XTENSA)
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} // namespace tflite
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#endif // TENSORFLOW_LITE_MICRO_KERNELS_CONV_H_
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