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mirror of https://github.com/vee1e/tflite-micro - Infrastructure to enable deployment of ML models to low-powe
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David Davis 3d4cdc19fb
Add REDUCE_MIN to reduce kernel (#3113) 
@tensorflow/micro

Add the REDUCE_MiN operator to the reduce kernel.
Refactor reduce kernel to decrease number of methods in tflite namespace. Add REDUCE_MIN unit tests.
Fix unit test axis data to match tensor shape.
Make Xtensa reduce kernel use reference common code for REDUCE_MIN.
Update all op resolvers.

bug=fixes #3108
2025-08-05 22:11:17 +00:00
.github Fix mergify batch merge issue (duplicated) (#3165) 2025-08-01 16:31:08 -04:00
ci CI changes for REVERSE_V2 Operator (#3121) 2025-06-16 16:54:27 +00:00
codegen Remove deprecated BUILD tags (#3091) 2025-04-08 19:21:25 +00:00
data/continuous_builds
docs
python Add REDUCE_MIN to reduce kernel (#3113) 2025-08-05 22:11:17 +00:00
signal
tensorflow Add REDUCE_MIN to reduce kernel (#3113) 2025-08-05 22:11:17 +00:00
third_party Add REDUCE_MIN to reduce kernel (#3113) 2025-08-05 22:11:17 +00:00
tools
.bazelrc build(bazel): provide means of excluding whl_test locally (#2940) 2024-11-27 00:51:53 +00:00
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README.md

TensorFlow Lite for Microcontrollers

TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.

Additional Links:

Build Status

Official Builds

Build Type Status
CI (Linux) CI
Code Sync Sync from Upstream TF

Community Supported TFLM Examples

This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.

Platform Status
Arduino Arduino Antmicro
Coral Dev Board Micro TFLM + EdgeTPU Examples for Coral Dev Board Micro
Espressif Systems Dev Boards ESP Dev Boards
Renesas Boards TFLM Examples for Renesas Boards
Silicon Labs Dev Kits TFLM Examples for Silicon Labs Dev Kits
Sparkfun Edge Sparkfun Edge
Texas Instruments Dev Boards Texas Instruments Dev Boards

Community Supported Kernels and Unit Tests

This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.

Build Type Status
Cortex-M Cortex-M
Hexagon Hexagon
RISC-V RISC-V
Xtensa Xtensa
Generate Integration Test Generate Integration Test

Contributing

See our contribution documentation.

Getting Help

A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.

The following resources may also be useful:

  1. SIG Micro email group and monthly meetings.

  2. SIG Micro gitter chat room.

  3. For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.:

Additional Documentation

RFCs

  1. Pre-allocated tensors
  2. TensorFlow Lite for Microcontrollers Port of 16x8 Quantized Operators