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a37043ff7a
Confirmed that the following command passes: ``` ./tensorflow/lite/micro/tools/ci_build/test_all_new.sh GITHUB_PRESUBMIT ```
221 lines
10 KiB
C++
221 lines
10 KiB
C++
/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_CONV_H_
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#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_CONV_H_
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#include "tensorflow/lite/kernels/internal/common.h"
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namespace tflite {
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namespace reference_integer_ops {
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// Fixed-point per-channel-quantization convolution reference kernel.
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inline void ConvPerChannel(
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const ConvParams& params, const int32_t* output_multiplier,
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const int32_t* output_shift, const RuntimeShape& input_shape,
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const int8_t* input_data, const RuntimeShape& filter_shape,
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const int8_t* filter_data, const RuntimeShape& bias_shape,
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const int32_t* bias_data, const RuntimeShape& output_shape,
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int8_t* output_data) {
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// Get parameters.
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const int32_t input_offset = params.input_offset; // r = s(q - Z)
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const int stride_width = params.stride_width;
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const int stride_height = params.stride_height;
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const int dilation_width_factor = params.dilation_width_factor;
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const int dilation_height_factor = params.dilation_height_factor;
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const int pad_width = params.padding_values.width;
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const int pad_height = params.padding_values.height;
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const int32_t output_offset = params.output_offset;
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// Set min and max value of the output.
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const int32_t output_activation_min = params.quantized_activation_min;
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const int32_t output_activation_max = params.quantized_activation_max;
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// Consistency check.
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TFLITE_DCHECK_LE(output_activation_min, output_activation_max);
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TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4);
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TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4);
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TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4);
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const int batches = MatchingDim(input_shape, 0, output_shape, 0);
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const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3);
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const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3);
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if (bias_data) {
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TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth);
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}
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// Check dimensions of the tensors.
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const int input_height = input_shape.Dims(1);
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const int input_width = input_shape.Dims(2);
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const int filter_height = filter_shape.Dims(1);
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const int filter_width = filter_shape.Dims(2);
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const int output_height = output_shape.Dims(1);
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const int output_width = output_shape.Dims(2);
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for (int batch = 0; batch < batches; ++batch) {
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for (int out_y = 0; out_y < output_height; ++out_y) {
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const int in_y_origin = (out_y * stride_height) - pad_height;
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for (int out_x = 0; out_x < output_width; ++out_x) {
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const int in_x_origin = (out_x * stride_width) - pad_width;
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for (int out_channel = 0; out_channel < output_depth; ++out_channel) {
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int32_t acc = 0;
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for (int filter_y = 0; filter_y < filter_height; ++filter_y) {
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const int in_y = in_y_origin + dilation_height_factor * filter_y;
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for (int filter_x = 0; filter_x < filter_width; ++filter_x) {
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const int in_x = in_x_origin + dilation_width_factor * filter_x;
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// Zero padding by omitting the areas outside the image.
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const bool is_point_inside_image =
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(in_x >= 0) && (in_x < input_width) && (in_y >= 0) &&
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(in_y < input_height);
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if (!is_point_inside_image) {
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continue;
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}
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for (int in_channel = 0; in_channel < input_depth; ++in_channel) {
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int32_t input_val = input_data[Offset(input_shape, batch, in_y,
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in_x, in_channel)];
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int32_t filter_val = filter_data[Offset(
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filter_shape, out_channel, filter_y, filter_x, in_channel)];
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// Accumulate with 32 bits accumulator.
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// In the nudging process during model quantization, we force
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// real value of 0.0 be represented by a quantized value. This
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// guarantees that the input_offset is a int8_t, even though
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// it is represented using int32_t. int32_t += int8_t *
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// (int8_t - int8_t) so the highest value we can get from each
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// accumulation is [-127, 127] * ([-128, 127] -
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// [-128, 127]), which is [-32512, 32512]. log2(32512)
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// = 14.98, which means we can accumulate at least 2^16
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// multiplications without overflow. The accumulator is
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// applied to a filter so the accumulation logic will hold as
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// long as the filter size (filter_y * filter_x * in_channel)
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// does not exceed 2^16, which is the case in all the models
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// we have seen so far.
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// TODO(b/174275578): Add a check to make sure the
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// accumulator depth is smaller than 2^16.
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acc += filter_val * (input_val + input_offset);
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}
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}
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}
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if (bias_data) {
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acc += bias_data[out_channel];
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}
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acc = MultiplyByQuantizedMultiplier(
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acc, output_multiplier[out_channel], output_shift[out_channel]);
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acc += output_offset;
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acc = std::max(acc, output_activation_min);
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acc = std::min(acc, output_activation_max);
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output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] =
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static_cast<int8_t>(acc);
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}
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}
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}
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}
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}
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// Fixed-point per-channel-quantization convolution reference kernel.
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// 16-bit data and 8-bit filter
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inline void ConvPerChannel(
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const ConvParams& params, const int32_t* output_multiplier,
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const int32_t* output_shift, const RuntimeShape& input_shape,
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const int16_t* input_data, const RuntimeShape& filter_shape,
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const int8_t* filter_data, const RuntimeShape& bias_shape,
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const std::int64_t* bias_data, const RuntimeShape& output_shape,
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int16_t* output_data) {
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// Get parameters.
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const int stride_width = params.stride_width;
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const int stride_height = params.stride_height;
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const int dilation_width_factor = params.dilation_width_factor;
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const int dilation_height_factor = params.dilation_height_factor;
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const int pad_width = params.padding_values.width;
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const int pad_height = params.padding_values.height;
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// Set min and max value of the output.
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const int32_t output_activation_min = params.quantized_activation_min;
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const int32_t output_activation_max = params.quantized_activation_max;
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// Consistency check.
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TFLITE_DCHECK_LE(output_activation_min, output_activation_max);
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TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4);
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TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4);
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TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4);
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const int batches = MatchingDim(input_shape, 0, output_shape, 0);
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const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3);
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const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3);
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if (bias_data) {
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TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth);
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}
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// Check dimensions of the tensors.
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const int input_height = input_shape.Dims(1);
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const int input_width = input_shape.Dims(2);
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const int filter_height = filter_shape.Dims(1);
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const int filter_width = filter_shape.Dims(2);
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const int output_height = output_shape.Dims(1);
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const int output_width = output_shape.Dims(2);
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for (int batch = 0; batch < batches; ++batch) {
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for (int out_y = 0; out_y < output_height; ++out_y) {
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const int in_y_origin = (out_y * stride_height) - pad_height;
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for (int out_x = 0; out_x < output_width; ++out_x) {
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const int in_x_origin = (out_x * stride_width) - pad_width;
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for (int out_channel = 0; out_channel < output_depth; ++out_channel) {
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std::int64_t acc = 0;
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for (int filter_y = 0; filter_y < filter_height; ++filter_y) {
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const int in_y = in_y_origin + dilation_height_factor * filter_y;
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for (int filter_x = 0; filter_x < filter_width; ++filter_x) {
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const int in_x = in_x_origin + dilation_width_factor * filter_x;
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// Zero padding by omitting the areas outside the image.
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const bool is_point_inside_image =
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(in_x >= 0) && (in_x < input_width) && (in_y >= 0) &&
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(in_y < input_height);
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if (!is_point_inside_image) {
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continue;
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}
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for (int in_channel = 0; in_channel < input_depth; ++in_channel) {
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int32_t input_val = input_data[Offset(input_shape, batch, in_y,
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in_x, in_channel)];
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int32_t filter_val = filter_data[Offset(
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filter_shape, out_channel, filter_y, filter_x, in_channel)];
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// Accumulate with 64 bits accumulator.
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// int64_t += int8_t * int16_t so the highest value we can
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// get from each accumulation is [-127, 127] * ([-32768,
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// 32767] -
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// [-32768, 32767]), which is [-8322945, 8322945].
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// log2(8322945) = 22.99.
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acc += filter_val * input_val;
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}
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}
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}
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if (bias_data) {
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acc += bias_data[out_channel];
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}
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int32_t scaled_acc = MultiplyByQuantizedMultiplier(
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acc, output_multiplier[out_channel], output_shift[out_channel]);
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scaled_acc = std::max(scaled_acc, output_activation_min);
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scaled_acc = std::min(scaled_acc, output_activation_max);
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output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] =
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static_cast<int16_t>(scaled_acc);
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}
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}
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}
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}
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}
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} // namespace reference_integer_ops
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} // namespace tflite
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#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_CONV_H_
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